pci_regs.h
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006: <mj@ucw.cz>
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008:
009: http://www.pcisig.com/
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016:
017: http://www.hypertransport.org
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021:
022: #ifndef LINUX_PCI_REGS_H
023: #define LINUX_PCI_REGS_H
024:
025:
026:
027:
028:
029: #define PCI_VENDOR_ID 0x00
030: #define PCI_DEVICE_ID 0x02
031: #define PCI_COMMAND 0x04
032: #define PCI_COMMAND_IO 0x1
033: #define PCI_COMMAND_MEMORY 0x2
034: #define PCI_COMMAND_MASTER 0x4
035: #define PCI_COMMAND_SPECIAL 0x8
036: #define PCI_COMMAND_INVALIDATE 0x10
037: #define PCI_COMMAND_VGA_PALETTE 0x20
038: #define PCI_COMMAND_PARITY 0x40
039: #define PCI_COMMAND_WAIT 0x80
040: #define PCI_COMMAND_SERR 0x100
041: #define PCI_COMMAND_FAST_BACK 0x200
042: #define PCI_COMMAND_INTX_DISABLE 0x400
043:
044: #define PCI_STATUS 0x06
045: #define PCI_STATUS_INTERRUPT 0x08
046: #define PCI_STATUS_CAP_LIST 0x10
047: #define PCI_STATUS_66MHZ 0x20
048: #define PCI_STATUS_UDF 0x40
049: #define PCI_STATUS_FAST_BACK 0x80
050: #define PCI_STATUS_PARITY 0x100
051: #define PCI_STATUS_DEVSEL_MASK 0x600
052: #define PCI_STATUS_DEVSEL_FAST 0x000
053: #define PCI_STATUS_DEVSEL_MEDIUM 0x200
054: #define PCI_STATUS_DEVSEL_SLOW 0x400
055: #define PCI_STATUS_SIG_TARGET_ABORT 0x800
056: #define PCI_STATUS_REC_TARGET_ABORT 0x1000
057: #define PCI_STATUS_REC_MASTER_ABORT 0x2000
058: #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000
059: #define PCI_STATUS_DETECTED_PARITY 0x8000
060:
061: #define PCI_CLASS_REVISION 0x08
062: #define PCI_REVISION_ID 0x08
063: #define PCI_CLASS_PROG 0x09
064: #define PCI_CLASS_DEVICE 0x0a
065:
066: #define PCI_CACHE_LINE_SIZE 0x0c
067: #define PCI_LATENCY_TIMER 0x0d
068: #define PCI_HEADER_TYPE 0x0e
069: #define PCI_HEADER_TYPE_NORMAL 0
070: #define PCI_HEADER_TYPE_BRIDGE 1
071: #define PCI_HEADER_TYPE_CARDBUS 2
072:
073: #define PCI_BIST 0x0f
074: #define PCI_BIST_CODE_MASK 0x0f
075: #define PCI_BIST_START 0x40
076: #define PCI_BIST_CAPABLE 0x80
077:
078:
079:
080:
081:
082:
083:
084: #define PCI_BASE_ADDRESS_0 0x10
085: #define PCI_BASE_ADDRESS_1 0x14
086: #define PCI_BASE_ADDRESS_2 0x18
087: #define PCI_BASE_ADDRESS_3 0x1c
088: #define PCI_BASE_ADDRESS_4 0x20
089: #define PCI_BASE_ADDRESS_5 0x24
090: #define PCI_BASE_ADDRESS_SPACE 0x01
091: #define PCI_BASE_ADDRESS_SPACE_IO 0x01
092: #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
093: #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
094: #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00
095: #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02
096: #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04
097: #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08
098: #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
099: #define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
100:
101:
102:
103: #define PCI_CARDBUS_CIS 0x28
104: #define PCI_SUBSYSTEM_VENDOR_ID 0x2c
105: #define PCI_SUBSYSTEM_ID 0x2e
106: #define PCI_ROM_ADDRESS 0x30
107: #define PCI_ROM_ADDRESS_ENABLE 0x01
108: #define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
109:
110: #define PCI_CAPABILITY_LIST 0x34
111:
112:
113: #define PCI_INTERRUPT_LINE 0x3c
114: #define PCI_INTERRUPT_PIN 0x3d
115: #define PCI_MIN_GNT 0x3e
116: #define PCI_MAX_LAT 0x3f
117:
118:
119: #define PCI_PRIMARY_BUS 0x18
120: #define PCI_SECONDARY_BUS 0x19
121: #define PCI_SUBORDINATE_BUS 0x1a
122: #define PCI_SEC_LATENCY_TIMER 0x1b
123: #define PCI_IO_BASE 0x1c
124: #define PCI_IO_LIMIT 0x1d
125: #define PCI_IO_RANGE_TYPE_MASK 0x0fUL
126: #define PCI_IO_RANGE_TYPE_16 0x00
127: #define PCI_IO_RANGE_TYPE_32 0x01
128: #define PCI_IO_RANGE_MASK (~0x0fUL)
129: #define PCI_SEC_STATUS 0x1e
130: #define PCI_MEMORY_BASE 0x20
131: #define PCI_MEMORY_LIMIT 0x22
132: #define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL
133: #define PCI_MEMORY_RANGE_MASK (~0x0fUL)
134: #define PCI_PREF_MEMORY_BASE 0x24
135: #define PCI_PREF_MEMORY_LIMIT 0x26
136: #define PCI_PREF_RANGE_TYPE_MASK 0x0fUL
137: #define PCI_PREF_RANGE_TYPE_32 0x00
138: #define PCI_PREF_RANGE_TYPE_64 0x01
139: #define PCI_PREF_RANGE_MASK (~0x0fUL)
140: #define PCI_PREF_BASE_UPPER32 0x28
141: #define PCI_PREF_LIMIT_UPPER32 0x2c
142: #define PCI_IO_BASE_UPPER16 0x30
143: #define PCI_IO_LIMIT_UPPER16 0x32
144:
145:
146: #define PCI_ROM_ADDRESS1 0x38
147:
148: #define PCI_BRIDGE_CONTROL 0x3e
149: #define PCI_BRIDGE_CTL_PARITY 0x01
150: #define PCI_BRIDGE_CTL_SERR 0x02
151: #define PCI_BRIDGE_CTL_ISA 0x04
152: #define PCI_BRIDGE_CTL_VGA 0x08
153: #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20
154: #define PCI_BRIDGE_CTL_BUS_RESET 0x40
155: #define PCI_BRIDGE_CTL_FAST_BACK 0x80
156:
157:
158: #define PCI_CB_CAPABILITY_LIST 0x14
159:
160: #define PCI_CB_SEC_STATUS 0x16
161: #define PCI_CB_PRIMARY_BUS 0x18
162: #define PCI_CB_CARD_BUS 0x19
163: #define PCI_CB_SUBORDINATE_BUS 0x1a
164: #define PCI_CB_LATENCY_TIMER 0x1b
165: #define PCI_CB_MEMORY_BASE_0 0x1c
166: #define PCI_CB_MEMORY_LIMIT_0 0x20
167: #define PCI_CB_MEMORY_BASE_1 0x24
168: #define PCI_CB_MEMORY_LIMIT_1 0x28
169: #define PCI_CB_IO_BASE_0 0x2c
170: #define PCI_CB_IO_BASE_0_HI 0x2e
171: #define PCI_CB_IO_LIMIT_0 0x30
172: #define PCI_CB_IO_LIMIT_0_HI 0x32
173: #define PCI_CB_IO_BASE_1 0x34
174: #define PCI_CB_IO_BASE_1_HI 0x36
175: #define PCI_CB_IO_LIMIT_1 0x38
176: #define PCI_CB_IO_LIMIT_1_HI 0x3a
177: #define PCI_CB_IO_RANGE_MASK (~0x03UL)
178:
179: #define PCI_CB_BRIDGE_CONTROL 0x3e
180: #define PCI_CB_BRIDGE_CTL_PARITY 0x01
181: #define PCI_CB_BRIDGE_CTL_SERR 0x02
182: #define PCI_CB_BRIDGE_CTL_ISA 0x04
183: #define PCI_CB_BRIDGE_CTL_VGA 0x08
184: #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
185: #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40
186: #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80
187: #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100
188: #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
189: #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
190: #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
191: #define PCI_CB_SUBSYSTEM_ID 0x42
192: #define PCI_CB_LEGACY_MODE_BASE 0x44
193:
194:
195:
196:
197: #define PCI_CAP_LIST_ID 0
198: #define PCI_CAP_ID_PM 0x01
199: #define PCI_CAP_ID_AGP 0x02
200: #define PCI_CAP_ID_VPD 0x03
201: #define PCI_CAP_ID_SLOTID 0x04
202: #define PCI_CAP_ID_MSI 0x05
203: #define PCI_CAP_ID_CHSWP 0x06
204: #define PCI_CAP_ID_PCIX 0x07
205: #define PCI_CAP_ID_HT 0x08
206: #define PCI_CAP_ID_VNDR 0x09
207: #define PCI_CAP_ID_DBG 0x0A
208: #define PCI_CAP_ID_CCRC 0x0B
209: #define PCI_CAP_ID_SHPC 0x0C
210: #define PCI_CAP_ID_SSVID 0x0D
211: #define PCI_CAP_ID_AGP3 0x0E
212: #define PCI_CAP_ID_EXP 0x10
213: #define PCI_CAP_ID_MSIX 0x11
214: #define PCI_CAP_ID_AF 0x13
215: #define PCI_CAP_LIST_NEXT 1
216: #define PCI_CAP_FLAGS 2
217: #define PCI_CAP_SIZEOF 4
218:
219:
220:
221: #define PCI_PM_PMC 2
222: #define PCI_PM_CAP_VER_MASK 0x0007
223: #define PCI_PM_CAP_PME_CLOCK 0x0008
224: #define PCI_PM_CAP_RESERVED 0x0010
225: #define PCI_PM_CAP_DSI 0x0020
226: #define PCI_PM_CAP_AUX_POWER 0x01C0
227: #define PCI_PM_CAP_D1 0x0200
228: #define PCI_PM_CAP_D2 0x0400
229: #define PCI_PM_CAP_PME 0x0800
230: #define PCI_PM_CAP_PME_MASK 0xF800
231: #define PCI_PM_CAP_PME_D0 0x0800
232: #define PCI_PM_CAP_PME_D1 0x1000
233: #define PCI_PM_CAP_PME_D2 0x2000
234: #define PCI_PM_CAP_PME_D3 0x4000
235: #define PCI_PM_CAP_PME_D3cold 0x8000
236: #define PCI_PM_CAP_PME_SHIFT 11
237: #define PCI_PM_CTRL 4
238: #define PCI_PM_CTRL_STATE_MASK 0x0003
239: #define PCI_PM_CTRL_NO_SOFT_RESET 0x0008
240: #define PCI_PM_CTRL_PME_ENABLE 0x0100
241: #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00
242: #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000
243: #define PCI_PM_CTRL_PME_STATUS 0x8000
244: #define PCI_PM_PPB_EXTENSIONS 6
245: #define PCI_PM_PPB_B2_B3 0x40
246: #define PCI_PM_BPCC_ENABLE 0x80
247: #define PCI_PM_DATA_REGISTER 7
248: #define PCI_PM_SIZEOF 8
249:
250:
251:
252: #define PCI_AGP_VERSION 2
253: #define PCI_AGP_RFU 3
254: #define PCI_AGP_STATUS 4
255: #define PCI_AGP_STATUS_RQ_MASK 0xff000000
256: #define PCI_AGP_STATUS_SBA 0x0200
257: #define PCI_AGP_STATUS_64BIT 0x0020
258: #define PCI_AGP_STATUS_FW 0x0010
259: #define PCI_AGP_STATUS_RATE4 0x0004
260: #define PCI_AGP_STATUS_RATE2 0x0002
261: #define PCI_AGP_STATUS_RATE1 0x0001
262: #define PCI_AGP_COMMAND 8
263: #define PCI_AGP_COMMAND_RQ_MASK 0xff000000
264: #define PCI_AGP_COMMAND_SBA 0x0200
265: #define PCI_AGP_COMMAND_AGP 0x0100
266: #define PCI_AGP_COMMAND_64BIT 0x0020
267: #define PCI_AGP_COMMAND_FW 0x0010
268: #define PCI_AGP_COMMAND_RATE4 0x0004
269: #define PCI_AGP_COMMAND_RATE2 0x0002
270: #define PCI_AGP_COMMAND_RATE1 0x0001
271: #define PCI_AGP_SIZEOF 12
272:
273:
274:
275: #define PCI_VPD_ADDR 2
276: #define PCI_VPD_ADDR_MASK 0x7fff
277: #define PCI_VPD_ADDR_F 0x8000
278: #define PCI_VPD_DATA 4
279:
280:
281:
282: #define PCI_SID_ESR 2
283: #define PCI_SID_ESR_NSLOTS 0x1f
284: #define PCI_SID_ESR_FIC 0x20
285: #define PCI_SID_CHASSIS_NR 3
286:
287:
288:
289: #define PCI_MSI_FLAGS 2
290: #define PCI_MSI_FLAGS_64BIT 0x80
291: #define PCI_MSI_FLAGS_QSIZE 0x70
292: #define PCI_MSI_FLAGS_QMASK 0x0e
293: #define PCI_MSI_FLAGS_ENABLE 0x01
294: #define PCI_MSI_FLAGS_MASKBIT 0x100
295: #define PCI_MSI_RFU 3
296: #define PCI_MSI_ADDRESS_LO 4
297: #define PCI_MSI_ADDRESS_HI 8
298: #define PCI_MSI_DATA_32 8
299: #define PCI_MSI_MASK_32 12
300: #define PCI_MSI_DATA_64 12
301: #define PCI_MSI_MASK_64 16
302:
303:
304: #define PCI_MSIX_FLAGS 2
305: #define PCI_MSIX_FLAGS_QSIZE 0x7FF
306: #define PCI_MSIX_FLAGS_ENABLE (1 << 15)
307: #define PCI_MSIX_FLAGS_MASKALL (1 << 14)
308: #define PCI_MSIX_TABLE 4
309: #define PCI_MSIX_PBA 8
310: #define PCI_MSIX_FLAGS_BIRMASK (7 << 0)
311:
312:
313: #define PCI_MSIX_ENTRY_SIZE 16
314: #define PCI_MSIX_ENTRY_LOWER_ADDR 0
315: #define PCI_MSIX_ENTRY_UPPER_ADDR 4
316: #define PCI_MSIX_ENTRY_DATA 8
317: #define PCI_MSIX_ENTRY_VECTOR_CTRL 12
318: #define PCI_MSIX_ENTRY_CTRL_MASKBIT 1
319:
320:
321:
322: #define PCI_CHSWP_CSR 2
323: #define PCI_CHSWP_DHA 0x01
324: #define PCI_CHSWP_EIM 0x02
325: #define PCI_CHSWP_PIE 0x04
326: #define PCI_CHSWP_LOO 0x08
327: #define PCI_CHSWP_PI 0x30
328: #define PCI_CHSWP_EXT 0x40
329: #define PCI_CHSWP_INS 0x80
330:
331:
332:
333: #define PCI_AF_LENGTH 2
334: #define PCI_AF_CAP 3
335: #define PCI_AF_CAP_TP 0x01
336: #define PCI_AF_CAP_FLR 0x02
337: #define PCI_AF_CTRL 4
338: #define PCI_AF_CTRL_FLR 0x01
339: #define PCI_AF_STATUS 5
340: #define PCI_AF_STATUS_TP 0x01
341:
342:
343:
344: #define PCI_X_CMD 2
345: #define PCI_X_CMD_DPERR_E 0x0001
346: #define PCI_X_CMD_ERO 0x0002
347: #define PCI_X_CMD_READ_512 0x0000
348: #define PCI_X_CMD_READ_1K 0x0004
349: #define PCI_X_CMD_READ_2K 0x0008
350: #define PCI_X_CMD_READ_4K 0x000c
351: #define PCI_X_CMD_MAX_READ 0x000c
352:
353: #define PCI_X_CMD_SPLIT_1 0x0000
354: #define PCI_X_CMD_SPLIT_2 0x0010
355: #define PCI_X_CMD_SPLIT_3 0x0020
356: #define PCI_X_CMD_SPLIT_4 0x0030
357: #define PCI_X_CMD_SPLIT_8 0x0040
358: #define PCI_X_CMD_SPLIT_12 0x0050
359: #define PCI_X_CMD_SPLIT_16 0x0060
360: #define PCI_X_CMD_SPLIT_32 0x0070
361: #define PCI_X_CMD_MAX_SPLIT 0x0070
362: #define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3)
363: #define PCI_X_STATUS 4
364: #define PCI_X_STATUS_DEVFN 0x000000ff
365: #define PCI_X_STATUS_BUS 0x0000ff00
366: #define PCI_X_STATUS_64BIT 0x00010000
367: #define PCI_X_STATUS_133MHZ 0x00020000
368: #define PCI_X_STATUS_SPL_DISC 0x00040000
369: #define PCI_X_STATUS_UNX_SPL 0x00080000
370: #define PCI_X_STATUS_COMPLEX 0x00100000
371: #define PCI_X_STATUS_MAX_READ 0x00600000
372: #define PCI_X_STATUS_MAX_SPLIT 0x03800000
373: #define PCI_X_STATUS_MAX_CUM 0x1c000000
374: #define PCI_X_STATUS_SPL_ERR 0x20000000
375: #define PCI_X_STATUS_266MHZ 0x40000000
376: #define PCI_X_STATUS_533MHZ 0x80000000
377:
378:
379:
380: #define PCI_SSVID_VENDOR_ID 4
381: #define PCI_SSVID_DEVICE_ID 6
382:
383:
384:
385: #define PCI_EXP_FLAGS 2
386: #define PCI_EXP_FLAGS_VERS 0x000f
387: #define PCI_EXP_FLAGS_TYPE 0x00f0
388: #define PCI_EXP_TYPE_ENDPOINT 0x0
389: #define PCI_EXP_TYPE_LEG_END 0x1
390: #define PCI_EXP_TYPE_ROOT_PORT 0x4
391: #define PCI_EXP_TYPE_UPSTREAM 0x5
392: #define PCI_EXP_TYPE_DOWNSTREAM 0x6
393: #define PCI_EXP_TYPE_PCI_BRIDGE 0x7
394: #define PCI_EXP_TYPE_RC_END 0x9
395: #define PCI_EXP_TYPE_RC_EC 0xa
396: #define PCI_EXP_FLAGS_SLOT 0x0100
397: #define PCI_EXP_FLAGS_IRQ 0x3e00
398: #define PCI_EXP_DEVCAP 4
399: #define PCI_EXP_DEVCAP_PAYLOAD 0x07
400: #define PCI_EXP_DEVCAP_PHANTOM 0x18
401: #define PCI_EXP_DEVCAP_EXT_TAG 0x20
402: #define PCI_EXP_DEVCAP_L0S 0x1c0
403: #define PCI_EXP_DEVCAP_L1 0xe00
404: #define PCI_EXP_DEVCAP_ATN_BUT 0x1000
405: #define PCI_EXP_DEVCAP_ATN_IND 0x2000
406: #define PCI_EXP_DEVCAP_PWR_IND 0x4000
407: #define PCI_EXP_DEVCAP_RBER 0x8000
408: #define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000
409: #define PCI_EXP_DEVCAP_PWR_SCL 0xc000000
410: #define PCI_EXP_DEVCAP_FLR 0x10000000
411: #define PCI_EXP_DEVCTL 8
412: #define PCI_EXP_DEVCTL_CERE 0x0001
413: #define PCI_EXP_DEVCTL_NFERE 0x0002
414: #define PCI_EXP_DEVCTL_FERE 0x0004
415: #define PCI_EXP_DEVCTL_URRE 0x0008
416: #define PCI_EXP_DEVCTL_RELAX_EN 0x0010
417: #define PCI_EXP_DEVCTL_PAYLOAD 0x00e0
418: #define PCI_EXP_DEVCTL_EXT_TAG 0x0100
419: #define PCI_EXP_DEVCTL_PHANTOM 0x0200
420: #define PCI_EXP_DEVCTL_AUX_PME 0x0400
421: #define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800
422: #define PCI_EXP_DEVCTL_READRQ 0x7000
423: #define PCI_EXP_DEVCTL_BCR_FLR 0x8000
424: #define PCI_EXP_DEVSTA 10
425: #define PCI_EXP_DEVSTA_CED 0x01
426: #define PCI_EXP_DEVSTA_NFED 0x02
427: #define PCI_EXP_DEVSTA_FED 0x04
428: #define PCI_EXP_DEVSTA_URD 0x08
429: #define PCI_EXP_DEVSTA_AUXPD 0x10
430: #define PCI_EXP_DEVSTA_TRPND 0x20
431: #define PCI_EXP_LNKCAP 12
432: #define PCI_EXP_LNKCAP_SLS 0x0000000f
433: #define PCI_EXP_LNKCAP_MLW 0x000003f0
434: #define PCI_EXP_LNKCAP_ASPMS 0x00000c00
435: #define PCI_EXP_LNKCAP_L0SEL 0x00007000
436: #define PCI_EXP_LNKCAP_L1EL 0x00038000
437: #define PCI_EXP_LNKCAP_CLKPM 0x00040000
438: #define PCI_EXP_LNKCAP_SDERC 0x00080000
439: #define PCI_EXP_LNKCAP_DLLLARC 0x00100000
440: #define PCI_EXP_LNKCAP_LBNC 0x00200000
441: #define PCI_EXP_LNKCAP_PN 0xff000000
442: #define PCI_EXP_LNKCTL 16
443: #define PCI_EXP_LNKCTL_ASPMC 0x0003
444: #define PCI_EXP_LNKCTL_RCB 0x0008
445: #define PCI_EXP_LNKCTL_LD 0x0010
446: #define PCI_EXP_LNKCTL_RL 0x0020
447: #define PCI_EXP_LNKCTL_CCC 0x0040
448: #define PCI_EXP_LNKCTL_ES 0x0080
449: #define PCI_EXP_LNKCTL_CLKREQ_EN 0x100
450: #define PCI_EXP_LNKCTL_HAWD 0x0200
451: #define PCI_EXP_LNKCTL_LBMIE 0x0400
452: #define PCI_EXP_LNKCTL_LABIE 0x0800
453: #define PCI_EXP_LNKSTA 18
454: #define PCI_EXP_LNKSTA_CLS 0x000f
455: #define PCI_EXP_LNKSTA_CLS_2_5GB 0x01
456: #define PCI_EXP_LNKSTA_CLS_5_0GB 0x02
457: #define PCI_EXP_LNKSTA_NLW 0x03f0
458: #define PCI_EXP_LNKSTA_NLW_SHIFT 4
459: #define PCI_EXP_LNKSTA_LT 0x0800
460: #define PCI_EXP_LNKSTA_SLC 0x1000
461: #define PCI_EXP_LNKSTA_DLLLA 0x2000
462: #define PCI_EXP_LNKSTA_LBMS 0x4000
463: #define PCI_EXP_LNKSTA_LABS 0x8000
464: #define PCI_EXP_SLTCAP 20
465: #define PCI_EXP_SLTCAP_ABP 0x00000001
466: #define PCI_EXP_SLTCAP_PCP 0x00000002
467: #define PCI_EXP_SLTCAP_MRLSP 0x00000004
468: #define PCI_EXP_SLTCAP_AIP 0x00000008
469: #define PCI_EXP_SLTCAP_PIP 0x00000010
470: #define PCI_EXP_SLTCAP_HPS 0x00000020
471: #define PCI_EXP_SLTCAP_HPC 0x00000040
472: #define PCI_EXP_SLTCAP_SPLV 0x00007f80
473: #define PCI_EXP_SLTCAP_SPLS 0x00018000
474: #define PCI_EXP_SLTCAP_EIP 0x00020000
475: #define PCI_EXP_SLTCAP_NCCS 0x00040000
476: #define PCI_EXP_SLTCAP_PSN 0xfff80000
477: #define PCI_EXP_SLTCTL 24
478: #define PCI_EXP_SLTCTL_ABPE 0x0001
479: #define PCI_EXP_SLTCTL_PFDE 0x0002
480: #define PCI_EXP_SLTCTL_MRLSCE 0x0004
481: #define PCI_EXP_SLTCTL_PDCE 0x0008
482: #define PCI_EXP_SLTCTL_CCIE 0x0010
483: #define PCI_EXP_SLTCTL_HPIE 0x0020
484: #define PCI_EXP_SLTCTL_AIC 0x00c0
485: #define PCI_EXP_SLTCTL_PIC 0x0300
486: #define PCI_EXP_SLTCTL_PCC 0x0400
487: #define PCI_EXP_SLTCTL_EIC 0x0800
488: #define PCI_EXP_SLTCTL_DLLSCE 0x1000
489: #define PCI_EXP_SLTSTA 26
490: #define PCI_EXP_SLTSTA_ABP 0x0001
491: #define PCI_EXP_SLTSTA_PFD 0x0002
492: #define PCI_EXP_SLTSTA_MRLSC 0x0004
493: #define PCI_EXP_SLTSTA_PDC 0x0008
494: #define PCI_EXP_SLTSTA_CC 0x0010
495: #define PCI_EXP_SLTSTA_MRLSS 0x0020
496: #define PCI_EXP_SLTSTA_PDS 0x0040
497: #define PCI_EXP_SLTSTA_EIS 0x0080
498: #define PCI_EXP_SLTSTA_DLLSC 0x0100
499: #define PCI_EXP_RTCTL 28
500: #define PCI_EXP_RTCTL_SECEE 0x01
501: #define PCI_EXP_RTCTL_SENFEE 0x02
502: #define PCI_EXP_RTCTL_SEFEE 0x04
503: #define PCI_EXP_RTCTL_PMEIE 0x08
504: #define PCI_EXP_RTCTL_CRSSVE 0x10
505: #define PCI_EXP_RTCAP 30
506: #define PCI_EXP_RTSTA 32
507: #define PCI_EXP_RTSTA_PME 0x10000
508: #define PCI_EXP_RTSTA_PENDING 0x20000
509: #define PCI_EXP_DEVCAP2 36
510: #define PCI_EXP_DEVCAP2_ARI 0x20
511: #define PCI_EXP_DEVCAP2_LTR 0x800
512: #define PCI_EXP_OBFF_MASK 0xc0000
513: #define PCI_EXP_OBFF_MSG 0x40000
514: #define PCI_EXP_OBFF_WAKE 0x80000
515: #define PCI_EXP_DEVCTL2 40
516: #define PCI_EXP_DEVCTL2_ARI 0x20
517: #define PCI_EXP_IDO_REQ_EN 0x100
518: #define PCI_EXP_IDO_CMP_EN 0x200
519: #define PCI_EXP_LTR_EN 0x400
520: #define PCI_EXP_OBFF_MSGA_EN 0x2000
521: #define PCI_EXP_OBFF_MSGB_EN 0x4000
522: #define PCI_EXP_OBFF_WAKE_EN 0x6000
523: #define PCI_EXP_LNKCTL2 48
524: #define PCI_EXP_SLTCTL2 56
525:
526:
527: #define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
528: #define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf)
529: #define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
530:
531: #define PCI_EXT_CAP_ID_ERR 1
532: #define PCI_EXT_CAP_ID_VC 2
533: #define PCI_EXT_CAP_ID_DSN 3
534: #define PCI_EXT_CAP_ID_PWR 4
535: #define PCI_EXT_CAP_ID_VNDR 11
536: #define PCI_EXT_CAP_ID_ACS 13
537: #define PCI_EXT_CAP_ID_ARI 14
538: #define PCI_EXT_CAP_ID_ATS 15
539: #define PCI_EXT_CAP_ID_SRIOV 16
540: #define PCI_EXT_CAP_ID_LTR 24
541:
542:
543: #define PCI_ERR_UNCOR_STATUS 4
544: #define PCI_ERR_UNC_TRAIN 0x00000001
545: #define PCI_ERR_UNC_DLP 0x00000010
546: #define PCI_ERR_UNC_POISON_TLP 0x00001000
547: #define PCI_ERR_UNC_FCP 0x00002000
548: #define PCI_ERR_UNC_COMP_TIME 0x00004000
549: #define PCI_ERR_UNC_COMP_ABORT 0x00008000
550: #define PCI_ERR_UNC_UNX_COMP 0x00010000
551: #define PCI_ERR_UNC_RX_OVER 0x00020000
552: #define PCI_ERR_UNC_MALF_TLP 0x00040000
553: #define PCI_ERR_UNC_ECRC 0x00080000
554: #define PCI_ERR_UNC_UNSUP 0x00100000
555: #define PCI_ERR_UNCOR_MASK 8
556:
557: #define PCI_ERR_UNCOR_SEVER 12
558:
559: #define PCI_ERR_COR_STATUS 16
560: #define PCI_ERR_COR_RCVR 0x00000001
561: #define PCI_ERR_COR_BAD_TLP 0x00000040
562: #define PCI_ERR_COR_BAD_DLLP 0x00000080
563: #define PCI_ERR_COR_REP_ROLL 0x00000100
564: #define PCI_ERR_COR_REP_TIMER 0x00001000
565: #define PCI_ERR_COR_MASK 20
566:
567: #define PCI_ERR_CAP 24
568: #define PCI_ERR_CAP_FEP(x) ((x) & 31)
569: #define PCI_ERR_CAP_ECRC_GENC 0x00000020
570: #define PCI_ERR_CAP_ECRC_GENE 0x00000040
571: #define PCI_ERR_CAP_ECRC_CHKC 0x00000080
572: #define PCI_ERR_CAP_ECRC_CHKE 0x00000100
573: #define PCI_ERR_HEADER_LOG 28
574: #define PCI_ERR_ROOT_COMMAND 44
575:
576: #define PCI_ERR_ROOT_CMD_COR_EN 0x00000001
577:
578: #define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002
579:
580: #define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004
581: #define PCI_ERR_ROOT_STATUS 48
582: #define PCI_ERR_ROOT_COR_RCV 0x00000001
583:
584: #define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002
585:
586: #define PCI_ERR_ROOT_UNCOR_RCV 0x00000004
587:
588: #define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008
589: #define PCI_ERR_ROOT_FIRST_FATAL 0x00000010
590: #define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020
591: #define PCI_ERR_ROOT_FATAL_RCV 0x00000040
592: #define PCI_ERR_ROOT_ERR_SRC 52
593:
594:
595: #define PCI_VC_PORT_REG1 4
596: #define PCI_VC_PORT_REG2 8
597: #define PCI_VC_PORT_CTRL 12
598: #define PCI_VC_PORT_STATUS 14
599: #define PCI_VC_RES_CAP 16
600: #define PCI_VC_RES_CTRL 20
601: #define PCI_VC_RES_STATUS 26
602:
603:
604: #define PCI_PWR_DSR 4
605: #define PCI_PWR_DATA 8
606: #define PCI_PWR_DATA_BASE(x) ((x) & 0xff)
607: #define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3)
608: #define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7)
609: #define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3)
610: #define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7)
611: #define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7)
612: #define PCI_PWR_CAP 12
613: #define PCI_PWR_CAP_BUDGET(x) ((x) & 1)
614:
615:
616:
617:
618:
619:
620:
621:
622:
623: #define HT_3BIT_CAP_MASK 0xE0
624: #define HT_CAPTYPE_SLAVE 0x00
625: #define HT_CAPTYPE_HOST 0x20
626:
627: #define HT_5BIT_CAP_MASK 0xF8
628: #define HT_CAPTYPE_IRQ 0x80
629: #define HT_CAPTYPE_REMAPPING_40 0xA0
630: #define HT_CAPTYPE_REMAPPING_64 0xA2
631: #define HT_CAPTYPE_UNITID_CLUMP 0x90
632: #define HT_CAPTYPE_EXTCONF 0x98
633: #define HT_CAPTYPE_MSI_MAPPING 0xA8
634: #define HT_MSI_FLAGS 0x02
635: #define HT_MSI_FLAGS_ENABLE 0x1
636: #define HT_MSI_FLAGS_FIXED 0x2
637: #define HT_MSI_FIXED_ADDR 0x00000000FEE00000ULL
638: #define HT_MSI_ADDR_LO 0x04
639: #define HT_MSI_ADDR_LO_MASK 0xFFF00000
640: #define HT_MSI_ADDR_HI 0x08
641: #define HT_CAPTYPE_DIRECT_ROUTE 0xB0
642: #define HT_CAPTYPE_VCSET 0xB8
643: #define HT_CAPTYPE_ERROR_RETRY 0xC0
644: #define HT_CAPTYPE_GEN3 0xD0
645: #define HT_CAPTYPE_PM 0xE0
646:
647:
648: #define PCI_ARI_CAP 0x04
649: #define PCI_ARI_CAP_MFVC 0x0001
650: #define PCI_ARI_CAP_ACS 0x0002
651: #define PCI_ARI_CAP_NFN(x) (((x) >> 8) & 0xff)
652: #define PCI_ARI_CTRL 0x06
653: #define PCI_ARI_CTRL_MFVC 0x0001
654: #define PCI_ARI_CTRL_ACS 0x0002
655: #define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7)
656:
657:
658: #define PCI_ATS_CAP 0x04
659: #define PCI_ATS_CAP_QDEP(x) ((x) & 0x1f)
660: #define PCI_ATS_MAX_QDEP 32
661: #define PCI_ATS_CTRL 0x06
662: #define PCI_ATS_CTRL_ENABLE 0x8000
663: #define PCI_ATS_CTRL_STU(x) ((x) & 0x1f)
664: #define PCI_ATS_MIN_STU 12
665:
666:
667: #define PCI_PRI_CAP 0x13
668: #define PCI_PRI_CONTROL_OFF 0x04
669: #define PCI_PRI_STATUS_OFF 0x06
670: #define PCI_PRI_ENABLE 0x0001
671: #define PCI_PRI_RESET 0x0002
672: #define PCI_PRI_STATUS_RF 0x0001
673: #define PCI_PRI_STATUS_UPRGI 0x0002
674: #define PCI_PRI_STATUS_STOPPED 0x0100
675: #define PCI_PRI_MAX_REQ_OFF 0x08
676: #define PCI_PRI_ALLOC_REQ_OFF 0x0c
677:
678:
679: #define PCI_PASID_CAP 0x1b
680: #define PCI_PASID_CAP_OFF 0x04
681: #define PCI_PASID_CONTROL_OFF 0x06
682: #define PCI_PASID_ENABLE 0x01
683: #define PCI_PASID_EXEC 0x02
684: #define PCI_PASID_PRIV 0x04
685:
686:
687: #define PCI_SRIOV_CAP 0x04
688: #define PCI_SRIOV_CAP_VFM 0x01
689: #define PCI_SRIOV_CAP_INTR(x) ((x) >> 21)
690: #define PCI_SRIOV_CTRL 0x08
691: #define PCI_SRIOV_CTRL_VFE 0x01
692: #define PCI_SRIOV_CTRL_VFM 0x02
693: #define PCI_SRIOV_CTRL_INTR 0x04
694: #define PCI_SRIOV_CTRL_MSE 0x08
695: #define PCI_SRIOV_CTRL_ARI 0x10
696: #define PCI_SRIOV_STATUS 0x0a
697: #define PCI_SRIOV_STATUS_VFM 0x01
698: #define PCI_SRIOV_INITIAL_VF 0x0c
699: #define PCI_SRIOV_TOTAL_VF 0x0e
700: #define PCI_SRIOV_NUM_VF 0x10
701: #define PCI_SRIOV_FUNC_LINK 0x12
702: #define PCI_SRIOV_VF_OFFSET 0x14
703: #define PCI_SRIOV_VF_STRIDE 0x16
704: #define PCI_SRIOV_VF_DID 0x1a
705: #define PCI_SRIOV_SUP_PGSIZE 0x1c
706: #define PCI_SRIOV_SYS_PGSIZE 0x20
707: #define PCI_SRIOV_BAR 0x24
708: #define PCI_SRIOV_NUM_BARS 6
709: #define PCI_SRIOV_VFM 0x3c
710: #define PCI_SRIOV_VFM_BIR(x) ((x) & 7)
711: #define PCI_SRIOV_VFM_OFFSET(x) ((x) & ~7)
712: #define PCI_SRIOV_VFM_UA 0x0
713: #define PCI_SRIOV_VFM_MI 0x1
714: #define PCI_SRIOV_VFM_MO 0x2
715: #define PCI_SRIOV_VFM_AV 0x3
716:
717: #define PCI_LTR_MAX_SNOOP_LAT 0x4
718: #define PCI_LTR_MAX_NOSNOOP_LAT 0x6
719: #define PCI_LTR_VALUE_MASK 0x000003ff
720: #define PCI_LTR_SCALE_MASK 0x00001c00
721: #define PCI_LTR_SCALE_SHIFT 10
722:
723:
724: #define PCI_ACS_CAP 0x04
725: #define PCI_ACS_SV 0x01
726: #define PCI_ACS_TB 0x02
727: #define PCI_ACS_RR 0x04
728: #define PCI_ACS_CR 0x08
729: #define PCI_ACS_UF 0x10
730: #define PCI_ACS_EC 0x20
731: #define PCI_ACS_DT 0x40
732: #define PCI_ACS_CTRL 0x06
733: #define PCI_ACS_EGRESS_CTL_V 0x08
734:
735: #endif
736:
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